module SHFT1(CLK,LOAD,DIN,QB);  output QB; input CLK,LOAD;  input[7:0] DIN; reg[7:0] REG8;  always @(posedge CLK)if(LOAD)REG8=DIN ;()else()=REG8[7:1];  assign QB = REG8[0] ;  endmodule空格处应该填入:


module SHFT1(CLK,LOAD,DIN,QB);  output QB; input CLK,LOAD;  input[7:0] DIN; reg[7:0] REG8;  always @(posedge CLK)if(LOAD)REG8=DIN ;()else()=REG8[7:1];  assign QB = REG8[0] ;  endmodule空格处应该填入:

A.LOAD

B.DIN

C.QB

D.REG8[6:0]

正确答案:REG8[6:0]


Tag:EDA技术与Verilog 空格 时间:2022-01-19 15:00:22